PSoC® 3は、構成可能なアナログおよびデジタル周辺機能、メモリ、マイクロコントローラを 1 つのチップに搭載した、真のプログラマブル組込み システム オン チップ です。それに加え、次のような特長の画期的な PSoC 3 新アーキテクチャにより、パフォーマンスも向上します。
- 分解能 20 ビットの高精度なアナログを統合
- プログラマブル PLD ベース ロジック
- シングルサイクル 8051 コア（最大 67 MHz）
PSoC 3 is now available in Chip Scale Packages (CSP) allowing you to design with the flexibility of PSoC in space constrained and small form factor applications like wearables, fitness products, and mobile devices.
The PSoC® architecture consists of configurable analog and digital blocks, a CPU subsystem and programmable routing and interconnect. PSoC lets you plug in predefined and tested IP from the PSoC library of functions, or code your own. Either way, you have the flexibility to build innovation and competitive advantage into your products.
Programable Routing & Interconnect
This frees you to re-route signals to userselected pins, shedding the constraints of a fixed-peripheral controller. In addition, global buses allow for signal multiplexing and logic operations, eliminating the need for a complicated digital-logic gate design.
Configurable Analog and Digital Blocks
The union of configurable analog and digital circuitry is the basis of the PSoC platform. You configure these blocks using pre-built library functions or by creating your own. By combining several digital blocks, you can create 16-, 24-, or even 32-bit wide logic resources. The analog blocks are composed of an assortment of switch capacitor, op-amp, comparator, ADC, DAC, and digital filter blocks, allowing complex analog signal flows. For a partial list of preconfigured functions included in PSoC software, see the sidebars on the next two pages. You can modify and personalize each function to your design.
PSoC offers a sophisticated CPU subsystem with SRAM , EE PROM, and flash memory, multiple core options and a variety of essential system resources including:
• Internal main and low-speed oscillator
• Connectivity to external crystal oscillator for precision, programmable clocking
• Sleep and watchdog timers
• Multiple clock sources that include a PLL
PSoC devices also have dedicated communication interfaces like I2C, Full-Speed USB 2.0, CAN 2.0, and on-chip debugging capabilities using JTAG and Serial Wire Debug. The newest members of the PSoC family offer industry-standard processors like the 8051 and Arm Cortex-M3.
Low Power Management Solutions with PSoC 3 and PSoC 5 devices are easy to design and implement because both families were designed for power optimization. PSoC 3 and PSoC 5 devices have flexible power modes to optimize power and performance.
- Best-in-class low power specifications plus industry leading CPU speed
- World’s widest voltage range, the only device that offers full analog capability below 1.8V
- Minimizes power by offloading CPU processing using on-chip programmable logic
- Integrated peripherals reduce total system level power
- PSoC Creator software provides easy to use APIs for quick power management
- Wide operating voltage range: 0.5V to 5.5V
- 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, 6.6 mA at 48 MHz
- 1 µA sleep mode with real-time clock and low voltage detect (LVD) interrupt
- 200 nA hibernate mode with SRAM retention
||Clock Sources Available
PICU, I2C, RTC,
|XRES, LVD, WDR
Full Analog Performance Across the Entire Voltage Range
PSoC 3 and PSoC 5 are the only devices on the market to offer full analog performance down to 0.5V allowing you to not only operate off of a single cell battery, but also a solar cell.