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TPACK Partners with Cypress on Reference Design for Ethernet Switches and Traffic Managers | サイプレス セミコンダクタ

TPACK Partners with Cypress on Reference Design for Ethernet Switches and Traffic Managers

最終更新日: 2013年12月13日

Springbank Reference Design Teams TPACK’s 40-Gbps Carrier Packet Engine
With Cypress’s High-Speed 65-nm QDR™II SRAMs

SAN JOSE, Calif., 2010年3月2日 – Cypress Semiconductor Corp. (NASDAQ: CY), the industry leader in SRAMs, and TPACK, an industry-leading provider of ICs that provide core data transport and switching functions, today announced a reference design for ultrafast Ethernet switches and queue management applications. The new Springbank reference design combines TPACK’s TPX4004 high-capacity integrated packet processor and traffic manager with Cypress’s CY7C15632KV18 72-Mbit Quad Data Rate™II (QDR™II ) SRAMs, offering the fastest available speeds with roadmaps for simple upgrades. The TPACK reference design also provides an easy interface to various FPGAs and is backed by robust application support.

TPACK’s high-reliability 40-Gbps TPX4004 provides true Metro Ethernet Forum (MEF)-defined, carrier-class performance. The extremely flexible, feature-rich layer 2 solution offers the ability to adapt to different system architectures and requirements. Cypress’s QDRII SRAMs are the industry’s first to go into high-volume production on 65-nm linewidth. The Cypress SRAMs feature the market’s fastest available clock speed of 550 MHz and a total data rate of 80 Gbps in a 36-bit I/O width QDRII device, using half the power of 90-nm SRAMs.

“Being first to market with this reference design demonstrates our technological leadership in high-throughput external memory solutions for carrier Ethernet switches and traffic managers,” said Thomas Rasmussen, Vice President of Product Line Management at TPACK. “Partnering with Cypress assures us of the highest performance and reliability from the industry’s leading SRAM supplier.”

“TPACK’s high-performance Springbank reference design is an excellent platform to showcase the blazing speeds of our 65-nm QDRII SRAMs in an advanced design for the networking market,” said David Kranzler, Vice President of Synchronous Memory and Timing Products at Cypress. “We look forward to working with TPACK on future projects, both with our SRAMS and our strong portfolio of timing solutions for networking applications.”

Compared with their 90-nm predecessors, Cypress’s 65-nm QDR and DDR SRAMs lower input and output capacitance by 60 percent. The QDRII and DDRII devices have On-Die Termination (ODT), which improves signal integrity, reduces system cost and saves board space by eliminating external termination resistors. The 65-nm devices use an advanced design and technology resulting in a 35 percent wider data valid window to reduce development time and cost for the customer. More info is available at https://www.cypress.com/go/syncSRAMs.


About TPACK
TPACK delivers cutting edge Silicon ICs providing core data transport and switching functions to leading Telecom and Networking equipment suppliers. TPACK’s SOFTSILICON products support the fastest deployment of new Carrier Class Packet and Optical Network standards, providing the most flexible, cost and power effective implementations throughout the life of the equipment. TPACK's customer base includes Tier 1 equipment providers who account for more than 50% of the optical transport equipment market.

TPACK is a privately held company headquartered in Copenhagen, Denmark, with offices in Palo Alto, California.

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Cypress, the Cypress logo, PSoC, PowerPSoC, CapSense and West Bridge are registered trademarks and QDR and TrueTouch are trademarks of Cypress Semiconductor Corp. All other trademarks are property of their owners.

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