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サイプレスが Cortex™-M3/PSoC® 設計コンテストの第一回目の期限を延長 | サイプレス セミコンダクタ

サイプレスが Cortex™-M3/PSoC® 設計コンテストの第一回目の期限を延長

最終更新日: 2011年1月11日

New Deadline for Schematics and Abstracts now 2011年1月24日
to Accommodate Exceptional Demand

San Jose, Calif., 2010年1月12日- Cypress Semiconductor Corp. (Nasdaq: CY), today extended the deadline for it’s ARM® Cortex™-M3/ PSoC® 5 Design Challenge. In order to accommodate exceptional demand, participants now have until 2011年1月24日 to complete stage one of the challenge. The design challenge aims to find the most innovative and useful designs from the millions of possibilities available to designers using the Cypress PSoC 5 architecture powered by the ARM Cortex-M3 processor.

A total of over $10,000 in cash and prizes will be awarded throughout the contest, including the $2,500 Grand Prize. More information, including how to enter the contest and how to become a judge, as well as lively interaction from participants and the engineering community is available at

Judging of the contest entries will be done in three stages:

  • Stage 1 – 2010年11月10日 to 2011年1月31日 - Designers will submit schematic block diagrams and abstracts of their ideas. From these entries, the top 100 will be selected, each of which will be awarded a free PSoC 5 Development Kit.
  • Stage 2 – 2011年1月31日 to 2011年4月4日 - The first round winners will then submit a video of their completed designs, along with a project file created in Cypress’s PSoC Creator IDE. From this group, four winners from the following categories will be selected and awarded: $1,000: Best Analog Design, Best Digital Design, Best PSoC Creator Component Design, and the Community Choice Design as selected by popular vote of the over 20,000 members of the Cypress Design Community.
  • Stage 3 – 2011年4月4日 to 2011年5月3日 - The Grand Prize will be selected from the four winning designs by an all-star panel of judges, including Cypress President and CEO, T.J. Rodgers; ARM Director of Enterprise and Embedded Solutions, Ian Ferguson; and Brian Fuller, Chief Product Strategist for EE Times.

“We’re pleased to see so much interest generated by this exciting contest,” said Matt Branda, Director of PSoC Platform Marketing. “We’re hopeful that even more engineers will be able to participate and truly make this contest competitive.”

Enter today at

About PSoC 5
The PSoC 5 architecture integrates a 32-bit ARM Cortex™-M3 core with high-precision programmable analog including 12-bit to 20-bit ADCs, digital logic libraries full of dozens of drop-in peripherals, best-in-class power management and rich connectivity resources. The PSoC Creator IDE introduces a unique schematic-based design methodology along with fully tested, pre-packaged analog and digital peripherals easily customizable through user-intuitive wizards and APIs to meet specific design requirements. More information on the PSoC platform is available at

サイプレスは、高パフォーマンス ミックスシグナルのプログラマブル ソリューションを提供し、製品化までの時間を短縮し、優れたシステム価値をもたらします。サイプレスが提供する製品には、フラッグシップであるPSoC® プログラマブル システム オン チップ ファミリや、その派生品で高電圧アプリケーションおよび LED 照明アプリケーション向けの PowerPSoC® ソリューションCapSense® タッチセンシング、タッチスクリーン向けの TrueTouch™ ソリューションなどがあります。サイプレスは、マルチメディア端末の接続性と性能を向上させる高性能 West Bridge® ソリューションを含むUSB コントローラにおける世界のリーダです。サイプレスは、高性能メモリおよびプログラマブルなタイミング デバイスにおいても市場でのリーダです。Cypress serves numerous markets, including consumer, mobile handsets, computation, data communications, automotive, industrial, and military. Cypress trades on the Nasdaq Global Select Market under the ticker symbol CY. Visit Cypress online at

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Cypress, the Cypress logo, PSoC, PowerPSoC, CapSense and West Bridge are registered trademarks and PSoC Creator and TrueTouch are trademarks of Cypress Semiconductor Corp. All other trademarks are property of their owners.


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