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UDB single bit to 8 bit IIR filter | サイプレス セミコンダクタ

UDB single bit to 8 bit IIR filter

Summary: 2 Replies, Latest post by JLS1 on 27 Mar 2013 06:00 PM PDT
Verified Answers: 0
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kees's picture
Cypress Employee
65 posts

 UDB Single Bit IIR filter




This memo introduces and distributes an IIR filter implemented in a UDB.  This component implements a first order IIR low pass filter.  It features 8 cutoff frequency choices (as a function of the sample clock rate, i.e. ~1/10*Fsample, to ~1/2000*Fsample), configurable output choices of: 2’s Compliment, Sign / Magnitude, Offset mode (0 – 254) and Absolute value.  The maximum output can be configured to saturate at +/- 127 all the way down to +/- 1.  The component has a configurable decimation rate to arbitrarily throw away 0 to 127 samples between outputs.  The filter outputs can also be staggered to provide ways for multiple filters to run in parallel without all the filters finishing at the same time.  The DMA wizard is aware of the output of this filter to facilitate easily configuring DMA to move data from the filter to some other location when the calculation is complete.  The filter is extremely fast, and completes 1 filter calculation in a minimum of 5 clocks (BETA of 0 and 2’s compliment output mode) and a maximum of 14 clocks (BETA of 7 and Sign/Mag, Offset or Absolute value output mode)


This filter can be used as a ‘decimator’ for an SC/CT based modulator when you desire an output sample rate equal to the modulator clock (not possible with a traditional CIC decimator) or if you wish to convert any single bit bitstream into a digital number from -127 to +127 through low pass filtering.  This could be used as a duty cycle measurement tool, or for any other creative use.  As an example, multiple instances of this component were used in conjunction with the SC/CT block modulator, LUT state machines, XOR gates and another special purpose datapath block to produce a 100% hardware based FSK demodulator.


This component is not "complete" in that it still lacks an official datasheet, but since I am not sure when I will get around to writing that, I felt that getting this into the community now (rather than never) was the best thing to do.  The ZIP archive includes the component, exported as a .cycomp archive, an example project, and a PDF file with lots of good information that can act as a stand-in for a datasheet.

user_200706552's picture
127 posts

 This is not working on Psoc5 chip ? Only Psoc3 ?

Only top half wave is working bottom half wave produce noise on my CY8C5588AXI.

Psoc5 not support datapath ?


Thanks help


user_200706552's picture
127 posts

Sorry all working fine !

My problem only bad offset on input signal :-)


Thanks this is great component :-)

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