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ユーザ モジュール データシート: Pulse Width Discriminator Data Sheet PWD V 1.0 (CY8C29/27/24/21xxx, CY8CLED02/04/08/16, CY8CLED0xD, CY8CLED0xG, CYWUSB69xx, CY8C21x45, CY8C22x45, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28xxx) | サイプレス セミコンダクタ

ユーザ モジュール データシート: Pulse Width Discriminator Data Sheet PWD V 1.0 (CY8C29/27/24/21xxx, CY8CLED02/04/08/16, CY8CLED0xD, CY8CLED0xG, CYWUSB69xx, CY8C21x45, CY8C22x45, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28xxx)

最終更新日: 
2014年5月22日
バージョン: 
1.0

特性および概要

  • Selectable input
  • Selectable output (with row interconnect)
  • Selectable clock, also it can run up to 48 MHz
  • Input signal is active low
  • Output signal is active low
  • Data input can be inverted
  • Data output can be inverted
     
The Pulse Width Discriminator (PWD) user module produces an output pulse and interrupt in response to an input pulse of certain duration. Input pulses less than specified are ignored. The main purpose of PWD is detecting signal preamble in the different communication protocols. Also it can be used as hardware signal debouncer.