Understanding Frequency Synthesis | サイプレス セミコンダクタ
Understanding Frequency Synthesis
Configuring a Phase Locked Loop (PLL) for a given frequency synthesis application can be, at the same time, both a quick and easy process as well as a time consuming, tedious, and iterative process. This dual nature in PLL system design arises from the number of loop parameters that need to be appropriately dialed in for a given application. As will be discussed in this article, there are two categories of loop parameters that must be considered: frequency synthesis parameters and performance parameters.