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Leveraging Cypress High-Performance FullFlex™ Dual-Port Interconnects In Next-Generation System Design | サイプレス セミコンダクタ

Leveraging Cypress High-Performance FullFlex™ Dual-Port Interconnects In Next-Generation System Design

最終更新日: 
2008 年 11 月 13 日

The increasing complexity in high-speed digital design creates a threat to timely system development, and therefore, to the success of the end product. Today's system architecture decisions are influenced not only by rapidly evolving families of processing elements, but also by time-to-market pressure. These challenges can be compounded in systems that have multiple processors on a single platform or multiple platforms entirely.

Dual-port interconnects have gained a reputation as highly flexible bridges between two independent sub-systems that do not have the ability to communicate with one another. In essence, the "apples" were able to talk to the "oranges." This created a greater freedom in component selection and enabled shortened design cycles. New dual-port interconnects provide much more than just a memory buffer between two processing elements. With ultra-wide data bus width and high clock speeds, new dual-port interconnects provide enough data throughput to support the most bandwidth-demanding applications.  New feature offerings such as variable impedance matching and deterministic access control also greatly simplify the development and debug of next generation, high-performance system designs.  To view more on this topic, click one of the download links above. 

翻訳版のドキュメントは参照用です。設計開発に携わっている場合には、英語版のドキュメントを参照されることをお勧めします。