S27KL0641/S27KS0641/S70KL1281/S70KS1281, 3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB), HyperRAM™ Self-Refresh DRAM | サイプレス セミコンダクタ
S27KL0641/S27KS0641/S70KL1281/S70KS1281, 3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB), HyperRAM™ Self-Refresh DRAM
HyperBus™ products use the high performance HyperBus for connection between a host system master and one or more slave interfaces. HyperBus is used to connect microprocessor, microcontroller, or ASIC devices with random access NOR Flash memory, RAM, or peripheral devices. HyperBus is an interface that draws upon the legacy features of both parallel and serial interface memories, while enhancing system performance, ease of design, and system cost reduction. Parallel flash and PSRAM have long been the standard for simple interface, high performance, random access memory, used for embedded system code execution and data storage. However, parallel interface memory requires a high signal count with separate control, address, and data connections that involve 45 or more signals. There have been parallel interface variations that reduce the signal count by multiplexing some address and data signals yet, may still involve 20 or more signals.
These high signal counts provide high data throughput but, at the cost of many connectors on the host system processor or ASIC and, higher cost multi-layer Printed Circuit Boards (PCB) that suffer from signal routing congestion. Many systems have moved to use of serial interface memories in order to reduce the number of signals needed for the connection to memory and to free up host system connections for use by other features or to reduce package and multi-layer PCB cost. However, serial memories generally have lower data throughput or longer random access time, which may relegate serial memories to the role of mainly transferring code and data to DRAM memory for random access and high throughput. But, such shadowing architectures cause a duplication of memory space that means paying twice for memory, once for non-volatile serial memory and again for additional DRAM to access the code and data during system operation.
HyperBus has a low signal count, Double Data Rate (DDR) interface, that achieves high read and write throughput while reducing the number of device I/O connections and signal routing congestion in a system. HyperBus memories provide the fast random access of a parallel interface, for code eXecution-in-Place (XiP) directly from flash memory, to reduce or eliminate duplication of memory space between non-volatile and volatile memories in the system.