You are here

S25FL256L/S25FL128L, 256 Mbit (32 Mbyte)/128 Mbit (16 Mbyte), 3.0 V FL-L Flash Memory | サイプレス セミコンダクタ

S25FL256L/S25FL128L, 256 Mbit (32 Mbyte)/128 Mbit (16 Mbyte), 3.0 V FL-L Flash Memory

最終更新日: 
2019年4月24日
バージョン: 
*H

The Cypress FL-L Family devices are Flash non-volatile memory products using: – Floating Gate technology – 65 nm process lithography The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase.

翻訳版のドキュメントは参照用です。設計開発に携わっている場合には、英語版のドキュメントを参照されることをお勧めします。