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CYF0018V, CYF0036V, CYF0072V: 18/36/72-Mbit Programmable FIFOs | サイプレス セミコンダクタ

CYF0018V, CYF0036V, CYF0072V: 18/36/72-Mbit Programmable FIFOs

最終更新日: 
2020年4月24日
バージョン: 
*S

18/36/72-Mbit Programmable FIFOs

特徴

  • Memory organization
    • Industry's largest first in first out (FIFO) memory densities: 18 Mbit, 36 Mbit, and 72 Mbit
    • Selectable memory organization: x9, x12, x16, x18, x20, x24, x32, x36
  • Up to 133-MHz clock operation
  • Unidirectional operation
  • Independent read and write ports
    • Supports simultaneous read and write operations
    • Reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock domains.
    • Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
  • 詳しくは、PDFをご覧ください。 

     

機能説明

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps.

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

For the full version of this message, please download the PDF version.

翻訳版のドキュメントは参照用です。設計開発に携わっている場合には、英語版のドキュメントを参照されることをお勧めします。