CY7C1648KV18, CY7C1650KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) | サイプレス セミコンダクタ
CY7C1648KV18, CY7C1650KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
- 144-Mbit density (8 M × 18, 4 M × 36)
- 450-MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
- Available in 2.0-clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Data valid pin (QVLD) to indicate valid data on the output
- Synchronous internally self-timed writes
- DDR II+ operates with 2.0-cycle read latency when DOFF is asserted high
The CY7C1648KV18, and CY7C1650KV18 are 1.8-V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two18-bit words (CY7C1648KV18), or 36-bit words (CY7C1650KV18) that burst sequentially into or out of the device.
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