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CY7C1548KV18, CY7C1550KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) | サイプレス セミコンダクタ

CY7C1548KV18, CY7C1550KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

最終更新日: 
2018 年 1 月 29 日
バージョン: 
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72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

特徴
  • 72 Mbit Density (4M x 18, 2M x 36)
  • 450 MHz Clock for High Bandwidth
  • 2-word Burst for reducing Address Bus Frequency
  • Double Data Rate (DDR) Interfaces (data transferred at 900 MHz) at 450 MHz
  • Available in 2.0 Clock Cycle Latency
  • Two Input Clocks (K and K) for precise DDR Timing
    • SRAM uses rising edges only
  • Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
  • Data Valid Pin (QVLD) to indicate Valid Data on the Output
  • 詳しくは、PDF をご覧ください。
     
 機能説明

The CY7C1548KV18, and CY7C1550KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words CY7C1548KV18), or 36-bit words (CY7C1550KV18) that burst sequentially into or out of the device.