CY7C1461AV33, CY7C1463AV33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture | サイプレス セミコンダクタ
CY7C1461AV33, CY7C1463AV33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture
最終更新日:
2020 年 6 月 09 日
バージョン：
*O
36 Mbit (1M x 36/2 M x 18) Flow-Through SRAM with NoBL™ Architecture
特徴
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No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
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Supports up to 133 MHz bus operations with zero wait states
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Data is transferred on every clock
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Pin compatible and functionally equivalent to ZBT™ devices
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Internally self timed output buffer control to eliminate the need to use OE
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Registered inputs for flow through operation
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Byte write capability
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3.3V and 2.5V I/O power supply
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Fast clock-to-output times
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6.5 ns (for 133 MHz device)
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詳しくは、PDF をご覧ください。
機能説明
The CY7C1461AV33/CY7C1463AV33 are 3.3 V, 1 M × 36/2 M × 18 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33 is equipped with the advanced NoBL logic required to enable consecutive read and write operations with data being transferred on every clock cycle.
関連ファイル
| ファイル名 | 言語 | サイズ | 最終更新日 |
|---|---|---|---|
 CY7C1461AV33, CY7C1463AV33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture Datasheet.pdf |
英語 | 639.43 KB | 06/04/2020 |