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CY7C1384D: 18-Mbit (512 K × 32) Pipelined SRAM | サイプレス セミコンダクタ

CY7C1384D: 18-Mbit (512 K × 32) Pipelined SRAM

最終更新日: 
2016 年 1 月 08 日
バージョン: 
*C

18-Mbit (512 K × 32) Pipelined SRAM

特徴

  • Supports bus operation up to 166 MHz
  • Available speed grades are 166 MHz
  • Registered inputs and outputs for pipelined operation
  • 3.3 V core power supply
  • 2.5 V or 3.3 V I/O power supply
  • Fast clock-to-output times
  • Provides high performance 3-1-1-1 access rate
  • 詳しくは、PDF をご覧ください。

機能説明

The CY7C1384D SRAM integrates 524,288 × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).