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CY7C1380D, CY7C1380F, CY7C1382D: 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM | サイプレス セミコンダクタ

CY7C1380D, CY7C1380F, CY7C1382D: 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM

最終更新日: 
2016 年 3 月 30 日
バージョン: 
*S

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

特徴

  • Supports bus operation up to 250 MHz
  • Available speed grades are 250, 200, and 167 MHz
  • Registered inputs and outputs for pipelined operation
  • 3.3V core power supply
  • 2.5V or 3.3V I/O power supply
  • Fast clock-to-output times
    • 2.6 ns (for 250 MHz device)
  • Provides high performance 3-1-1-1 access rate
  • User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • 詳しくは、PDF をご覧ください。

機能説明

The CY7C1380D/CY7C1380F/CY7C1382D SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.