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CY7C1370S/CY7C1372S, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture | サイプレス セミコンダクタ

CY7C1370S/CY7C1372S, 18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture

最終更新日: 
2016年4月15日
バージョン: 
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The CY7C1370S and CY7C1372S are 3.3 V, 512K × 36 and 1M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively.