You are here

CY7C1363D: 9-Mbit (512 K × 18) Flow-Through SRAM | サイプレス セミコンダクタ

CY7C1363D: 9-Mbit (512 K × 18) Flow-Through SRAM

最終更新日: 
2016 年 7 月 17 日
バージョン: 
*D

9-Mbit (512 K × 18) Flow-Through SRAM

特徴

  • Supports 133 MHz bus operations
  • 512 K × 18 common I/O
  • 3.3 V – 5% and +10% core power supply (VDD)
  • 2.5 V or 3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • Provide high performance 2-1-1-1 access rate
  • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • 詳しくは、PDF をご覧ください。

機能説明

The CY7C1363D is a 3.3 V, 512 K × 18 synchronous flow-through SRAM, respectively designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK).