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CY7C1355C, CY7C1357C: 9-Mbit (256 K × 36 / 512 K × 18) Flow-Through SRAM with NoBL™ Architecture | サイプレス セミコンダクタ

CY7C1355C, CY7C1357C: 9-Mbit (256 K × 36 / 512 K × 18) Flow-Through SRAM with NoBL™ Architecture

最終更新日: 
2020 年 6 月 08 日
バージョン: 
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9-Mbit (256 K × 36 / 512 K × 18) Flow-Through SRAM with NoBL™ Architecture

特徴

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
  • Can support up to 133-MHz bus operations with zero wait states
    • Data is transferred on every clock
  • Pin compatible and functionally equivalent to ZBT™ devices
  • Internally self-timed output buffer control to eliminate the need to use OE
  • Registered inputs for flow-through operation
  • Byte write capability
  • 3.3 V / 2.5 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • 詳しくは、PDF をご覧ください。
     

機能説明

The CY7C1355C/CY7C1357C is a 3.3 V, 256 K × 36 / 512 K × 18 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

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Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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