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CY7C1347G: 4-Mbit (128 K × 36) Pipelined Sync SRAM | サイプレス セミコンダクタ

CY7C1347G: 4-Mbit (128 K × 36) Pipelined Sync SRAM

最終更新日: 
2020 年 6 月 09 日
バージョン: 
*T

4-Mbit (128 K × 36) Pipelined Sync SRAM

特徴

  • Fully registered inputs and outputs for pipelined operation
  • 128 K × 36 common I/O architecture
  • 3.3 V core power supply (VDD)
  • 2.5- / 3.3-V I/O power supply (VDDQ)
  • Fast clock to output times: 2.6 ns (for 250 MHz device)
  • User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self timed writes
  • Asynchronous output enable
  • Offered in Pb-free 100-Pin TQFP, Pb-free 119-Ball BGA package
  • “ZZ” sleep mode option and stop clock option
  • Available in commercial temperature range

     

機能説明

The CY7C1347G is a 3.3 V, 128 K × 36 synchronous pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G I/O pins can operate at either the 2.5 V or the 3.3 V level. The I/O pins are 3.3 V tolerant when VDDQ = 2.5 V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250 MHz device).