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CY7C1318KV18, CY7C1320KV18: 18-Mbit DDR II SRAM Two-Word Burst Architecture | サイプレス セミコンダクタ

CY7C1318KV18, CY7C1320KV18: 18-Mbit DDR II SRAM Two-Word Burst Architecture

最終更新日: 
2018 年 1 月 29 日
バージョン: 
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18-Mbit DDR II SRAM Two-Word Burst Architecture

特徴

  • 18-Mbit density (1 M × 18, 512 K × 36)
  • 333-MHz clock for high bandwidth
  • Two-word burst for reducing address bus frequency
  • Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
  • 詳しくは、PDFをご覧ください。 
     

機能説明

The CY7C1318KV18, and CY7C1320KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

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