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CY7C1302DV25: 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture | サイプレス セミコンダクタ

CY7C1302DV25: 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

最終更新日: 
2017 年 11 月 30 日
バージョン: 
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9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

特徴

  • Separate independent Read and Write data ports
    • Supports concurrent transactions
  • 167-MHz clock for high bandwidth
    • 2.5 ns Clock-to-Valid access time
  • 2-word burst on all accesses
  • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz
  • Two input clocks (K and K) for precise DDR timing
    • SRAM uses rising edges only
  • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
  • 詳しくは、PDF をご覧ください。

機能説明

The CY7C1302DV25 is a 2.5 V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock.