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CY7C1011DV33: 2-Mbit (128 K × 16) Static RAM | サイプレス セミコンダクタ

CY7C1011DV33: 2-Mbit (128 K × 16) Static RAM

最終更新日: 
2018 年 10 月 09 日
バージョン: 
*H

2-Mbit (128 K × 16) Static RAM

特徴

  • Pin-and function-compatible with CY7C1011CV33
  • High speed
    • tAA = 10 ns
  • Low active power
    • ICC = 90 mA @ 10 ns (Industrial)
  • Low CMOS standby power
    • ISB2 = 10 mA
  • Data Retention at 2.0 V
  • Automatic power-down when deselected
  • Independent control of upper and lower bits
  • Easy memory expansion with CE and OE features
  • Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA

     

機能説明

The CY7C1011DV33 is a high-performance CMOS Static RAM organized as 128 K words by 16 bits.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16).