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CY2DP818: 1:8 Clock Fanout Buffer | サイプレス セミコンダクタ

CY2DP818: 1:8 Clock Fanout Buffer

2015 年 9 月 18 日

1:8 Clock Fanout Buffer


  • Low-voltage operation VDD = 3.3V
  • 1:8 fanout
  • Operation to 350 MHz
  • Single input configurable for LVDS, LVPECL, or LVTTL
  • 8 pair of LVPECL outputs
  • Drives a 50 ohm load
  • Low input capacitance
  • Low output skew
  • Low propagation delay (tpd = 4 ns, typical)
  • 商業的および産業的温度範囲
  • 38-Pin TSSOP Package
  • 詳しくは、PDF をご覧ください。


The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs.

Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock.

The CY2DP818 is ideal for both level translations from single ended to LVPECL and/or for the distribution of LVPECL based clock signals.

The Cypress CY2DP818 has configurable input functions. The input is user configurable via the InConfig pin for single ended or differential input.