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CY29352: 2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer | サイプレス セミコンダクタ

CY29352: 2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer

最終更新日: 
2020 年 6 月 08 日
バージョン: 
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2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer

特徴

  • Output frequency range: 16.67 MHz to 200 MHz
  • Input frequency range: 16.67 MHz to 200 MHz
  • 2.5Vまたは3.3V動作
  • Split 2.5V and 3.3V outputs
  • ±2% maximum output duty cycle variation
  • 11 clock outputs: drive up to 22 clock lines
  • LVCMOS reference clock input
  • 125 ps maximum output-output skew
  • PLL bypass mode
  • 詳しくは、PDF をご覧ください。
     

説明

The CY29352 is a low voltage high performance 200 MHz PLL based zero delay buffer designed for high speed clock distribution applications.

The CY29352 features an LVCMOS reference clock input and provides 11 outputs partitioned in three banks of five, four, and two outputs.