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CY23FP12: 200 MHz Field Programmable Zero Delay Buffer | サイプレス セミコンダクタ

CY23FP12: 200 MHz Field Programmable Zero Delay Buffer

最終更新日: 
2017 年 3 月 21 日
バージョン: 
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200 MHz Field Programmable Zero Delay Buffer

特徴

  • Fully Field-Programmable
    • Input and output dividers
    • Inverting/noninverting outputs
    • Phase-locked loop (PLL) or fanout buffer configu­ration
  • 10 MHz to 200 MHz Operating Range
  • Split 2.5V or 3.3V Outputs
  • Two LVCMOS Reference Inputs
  • Twelve Low Skew Outputs
    • 35 ps typical output-to-output skew (same frequency)
  • 詳しくは、PDF をご覧ください。
     

機能説明

The CY23FP12 is a high performance fully field-programmable 200 MHz zero delay buffer designed for high speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high performance ASICs and microprocessors.