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CY2305/CY2309, Low Cost 3.3 V Zero Delay Buffer | サイプレス セミコンダクタ

CY2305/CY2309, Low Cost 3.3 V Zero Delay Buffer

最終更新日: 
2020 年 7 月 02 日
バージョン: 
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Low Cost 3.3 V Zero Delay Buffer

特徴

  • 10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies
  • Zero input-output propagation delay
  • 60-ps typical cycle-to-cycle jitter (high drive)
  • Multiple low skew outputs
    • 85 ps typical output-to-output skew
    • One input drives five outputs (CY2305)
    • One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)
  • Compatible with Pentium-based systems
  • Test Mode to bypass phase-locked loop (PLL) (CY2309)
  • パッケージ:
    • 8-pin, 150-mil SOIC package (CY2305)
    • 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)
  • 3.3-V operation
  • 商業的および産業的温度範囲

     

機能説明

The CY2309 is a low-cost 3.3-V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100-/133 MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

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