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Sequencing Successive Approximation ADC (ADC_SAR_Seq) | サイプレス セミコンダクタ

Sequencing Successive Approximation ADC (ADC_SAR_Seq)

最終更新日: 
2018 年 3 月 20 日
バージョン: 
2.0
特徴
シンボル図
  • Supports PSoC 5LP devices
  • Selectable resolution (8, 10 or 12 bit) and sample rate (up to 1 Msps)
  • Scans up to 64 single ended or 32 differential channels automatically, or just a single input
     
ADC Chip

注: The actual maximum number of input channels depends on the number of routable analog GPIOs that are available on a specific PSoC part and package.

一般的な説明

The Sequencing SAR ADC component enables makes it possible for you to configure and then use the different operational modes of the SAR ADC on PSoC 5LP. You also have schematic level and firmware level support for seamless use of the Sequencing SAR ADC in PSoC Creator designs and projects. You are able to configure multiple analog channels that are automatically scanned with the results placed in individual SRAM locations.

翻訳版のドキュメントは参照用です。設計開発に携わっている場合には、英語版のドキュメントを参照されることをお勧めします。