Hardware Watchdog (PDL_HWWDG) | サイプレス セミコンダクタ
Hardware Watchdog (PDL_HWWDG)
The Hardware Watchdog is a 32-bit down counter that generates an interrupt, and optional reset, when the timer expires. The counter can be fed by a normally-functioning application to reset the counter and avoid the interrupt/reset. This enables the forced reset of a runaway application (one that fails to feed the watchdog).
The watchdog is clocked from the built-in low-speed CR oscillator (CLKLC) which enables the safe use of standby mode in your application. The counter automatically stops in the low power state and re-starts when the device wakes up.
HWWDG Component Parameter Editor