フィルタ | サイプレス セミコンダクタ

フィルタ

最終更新日: 
2018 年 11 月 20 日
バージョン: 
2.30
特徴

 
  • Easy filter configuration using the Digital Filter Block (DFB) available in select PSoC 3 and PSoC 5 LP devices
  • 2つの独立したフィルタ チャンネルをサポートし、それぞれが最大4つまでの設計ステージとしてカスケードできます。
  • Multiple FIR and IIR (Biquad) filter methods
  • Support for flexible coefficient entry
  • Final coefficient values available for further analysis
シンボル図

Filter 1 Image

一般的な説明

The Filter component allows easy creation of single or dual channel digital filters using the DFB. The component includes a filter design feature, which greatly simplifies the design and implementation processes. It supports two streaming channels that can be streamed directly from other hardware blocks (such as the ADC) using DMA. The filtered results can likewise be transferred using DMA, interrupts, or polling methods. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels, and this information is used to guide the choice of filter implementation. It reports (but does not set) the minimum bus clock frequency required to execute the filtering within the declared sample interval. This clock can then be set in the design-wide resource manager.

The Filter component supports many use cases. If something unusual occurs when using it, please report it (with a good description). Either email psoc_creator_feedback@cypress.com or contact tech support at https://www.cypress.com.



PSoC® Creatorフィルタ2.0コンポーネントビデオ

 

 
翻訳版のドキュメントは参照用です。設計開発に携わっている場合には、英語版のドキュメントを参照されることをお勧めします。