Dual Timer (PDL_DT) | サイプレス セミコンダクタ
Dual Timer (PDL_DT)
The DT Component enables easy setup of the Dual Timer block and its clock prescaler. The block is clocked by the APB bus clock (PCLK) and the prescaler allows each channel of the timer to divide the period by 1, 16, or 256. The channels operate independently of each other and can support 16- or 32-bit operation in three modes. Free running mode resets the internal counter to the maximum value each time that it reaches zero. Periodic mode uses a load register to reset the counter to a value provided by user firmware. One shot mode also support the programmable period but halts operation when the timer expires.
DT Component Parameter Editor