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AN89659 - Interfacing SPI F-RAM with PSoC® 4 | サイプレス セミコンダクタ

AN89659 - Interfacing SPI F-RAM with PSoC® 4

最終更新日: 
2020年5月30日
バージョン: 
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AN89659 shows how to interface Serial Peripheral Interface (SPI) F-RAM with Cypress's PSoC®4 (Programmable System-on-Chip) device with the help of example circuits, timing diagrams, and pseudo code. You can also use this application note as a reference design guide to interface SPI F-RAM with other standard SPI master controllers. This application note includes an associated PSoC 4 example project.

はじめに

The SPI F-RAM is a serial nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory (F-RAM) is a nonvolatile RAM that eliminates the complexities, overhead, and system-level reliability problems caused by serial EEPROM and other nonvolatile memories. Unlike serial EEPROM and flash memories, the F-RAM performs write operations at bus speed without incurring any write delays (NoDelay™). Data is directly written into the memory array, and the next bus cycle can begin immediately without the need for data polling. The F-RAM products offer a very high endurance of 1014, orders of magnitude higher than serial EEPROM and flash memories.

翻訳版のドキュメントは参照用です。設計開発に携わっている場合には、英語版のドキュメントを参照されることをお勧めします。