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AN89611 - PSoC® 3 and PSoC 5LP – Getting Started With Chip Scale Packages (CSP) | サイプレス セミコンダクタ

AN89611 - PSoC® 3 and PSoC 5LP – Getting Started With Chip Scale Packages (CSP)

最終更新日: 
2017年4月28日
バージョン: 
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This application note provides guidelines for using Cypress PSoC® 3 and PSoC 5LP devices in wafer-level chip scale packages (CSP). Included are instructions for using the I2C bootloader that is factory installed in these devices.

はじめに

Cypress is now offering its PSoC 3 and PSoC 5LP family of products in wafer-level chip scale packages (WLCSP, or CSP for short). These devices are designed to pack the maximum mixed-signal SoC capability per cubic millimeter. They feature package sizes as small as 4.25 × 4.98 × 0.6 mm to fit into tiny spaces on very small PCBs or flexible printed circuits (FPC). However, their small size mandates special manufacturing techniques and design considerations.

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

For the full version of this message, please download the PDF version.