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AN89371 - Power Saving With Cypress’s 65-nm Asynchronous PowerSnooze™ SRAM | サイプレス セミコンダクタ

AN89371 - Power Saving With Cypress’s 65-nm Asynchronous PowerSnooze™ SRAM

最終更新日: 
2015 年 8 月 26 日
バージョン: 
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This application note explains the PowerSnoozeTM feature of Cypress’ 65-nm Asynchronous Fast SRAM devices (CY7S10xxG family). PowerSnooze allows the SRAM to enter into a low-power mode during long chip disable periods. A user-controlled pin (DS) allows seamless transition between high-speed mode and low-power mode. This application note also describes the critical timing parameters for the mode transitions as well as a sample SRAM interface configuration to use the PowerSnooze feature in application systems.

はじめに

With the advent of mobile technology and portable battery-backed devices, power consumption has become one of the key factors in system design. System designers face the dilemma of selecting between faster operating speeds and lower power consumption for the microcontrollers/ASICs, peripherals, and memory devices in their systems.

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

For the full version of this message, please download the PDF version.

翻訳版のドキュメントは参照用です。設計開発に携わっている場合には、英語版のドキュメントを参照されることをお勧めします。