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AN84060 - QDR®-IV Design Guide | サイプレス セミコンダクタ

AN84060 - QDR®-IV Design Guide

最終更新日: 
2020 年 5 月 28 日
バージョン: 
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AN84060 describes the key features, functional description, operational modes, power calculation, and board design guidelines of QDR®-IV, Cypress’s quad data rate family of networking SRAMs. This application note also highlights the key differences among the QDR-II, QDR-II+, and QDR-IV SRAM family members.

はじめに

Streaming video, cloud services, and mobile data have fueled the continuing growth of global network traffic. To support this growth, the next generation of networking systems must provide faster line rates and process millions of packets every second. Packets arrive in a random order and each packet requires several memory transactions to process. In high-performance networking systems, the flow of packets demands hundreds of millions of memory transactions every second to look up routes from a forwarding table or to update statistics.

翻訳版のドキュメントは参照用です。設計開発に携わっている場合には、英語版のドキュメントを参照されることをお勧めします。