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AN64574 - Designing with Serial Peripheral Interface (SPI) nvSRAM | サイプレス セミコンダクタ

AN64574 - Designing with Serial Peripheral Interface (SPI) nvSRAM

最終更新日: 
2020年5月28日
バージョン: 
*I

Cypress’s serial peripheral interface (SPI) nvSRAM is a high-performance nonvolatile serial memory that offers zero cycle delay write operation and infinite SRAM write endurance. The SPI nvSRAM is a slave SPI device and requires an SPI master controller to access nvSRAM in a system. This application note provides a few key design considerations and firmware tips to guide the users designing with SPI nvSRAM. An associated project for PSoC 1 and a library component for PSoC 3 and PSoC 4 are also provided as an example project, which demonstrates SPI nvSRAM access by a standard SPI master controller.

SOC connection to SPI nvSRAM Diagram

翻訳版のドキュメントは参照用です。設計開発に携わっている場合には、英語版のドキュメントを参照されることをお勧めします。