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AN46982 - PLL Considerations in QDR® - II/II+/DDR-II/II+ SRAMs | サイプレス セミコンダクタ

AN46982 - PLL Considerations in QDR® - II/II+/DDR-II/II+ SRAMs

最終更新日: 
2020年5月28日
バージョン: 
*G

AN46982 provides an overview of the operation of QDR-II/II+/DDR-II/II+ SRAMs in PLL disabled mode.

はじめに

QDR SRAM family of devices has a phase-locked loop (PLL) within the device to synchronize the output data to the input clocks thereby enabling the device to operate at higher frequencies.

QDR-II/II+/DDR-II/II+ devices can be operated with PLL enabled or PLL disabled. This application note provides an overview of the operation of the device when the PLL is disabled.

PLL Off Diagram