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AN13553 - Using Processor Chip Enable as Address Valid Input to Antioch™ | サイプレス セミコンダクタ

AN13553 - Using Processor Chip Enable as Address Valid Input to Antioch™

最終更新日: 
2017 年 5 月 17 日
バージョン: 
*C
West Bridge® Antioch™ requires an Address Valid (ADV#) signal when the Processor Interface (P-Port) operates in asynchronous mode. Processors that do not have an ADV# signal (or any signal that can be programmed to behave like the ADV# signal) on their memory interface can use the information in this application note to interface to Antioch by connecting the processor’s Chip Enable signal to both the Chip Enable (CE#) signal and the ADV# signal on Antioch. This approach allows the designer to use Antioch with processors that may not have an ADV# signal whose timing is compatible with Antioch’s ADV# signal.